In charge trapping memory cells, which are nonvolatile memory cells based on charge storage between the channel region and/or the source/drain regions and the gate electrode, as part of the gate dielectric, a nonconductive storage layer is present between boundary layers for trapping charge carriers and thus for altering the programming state of the memory cell. Examples thereof include SONOS memory cells (semiconductor-oxide-nitride-oxide-semiconductor; see U.S. Pat. No. 5,768,192, U.S. Pat. No. 6,011,725, PCT Publication WO 99/60631), in which each boundary layer is an oxide and the storage layer is a nitride of the semiconductor material, usually silicon. Charge trapping memory cells are preferably programmed by channel hot electrons (CHE) and can be erased by means of hot holes from the channel region or by Fowler-Nordheim tunneling. An SONOS memory cell provided for a special mode of operation with a read voltage applied in the opposite sense to the programming process (reverse-read), the memory cell having a thickness of the boundary layers that is adapted to this mode of operation, has been referred to as an NROM memory cell (Boaz Eitan et al.: “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell” in IEEE Electron Device Letters 21, 543–545 (2000)).
The scalability of charge trapping memory cells is limited by the fact that, on account of the thicknesses of the dielectric layers required for data retention, i.e., of the storage layer between boundary layers, and owing to the high electrical voltages required, the channel length cannot be reduced in accordance with the minimum feature size possible. One approach to eliminate this problem consists in using a memory component in which the channel region is oriented vertically with respect to the top side of the silicon body and the channel length consequently does not limit the lateral dimensions of the memory cell and thus the required area of the top side of the semiconductor body. The top side of the semiconductor body has to be patterned suitably for such an arrangement of the channel region. This may be done by arranging the structure elements of the memory cell in elevated structures applied on the top side or in trenches in the semiconductor body.
For multi-bit charge trapping memory cells, in particular, in which at least two bits are stored, the variant with a trench transistor is a promising option for reducing the component area taken up. In the case of such a memory cell, the gate electrode is situated in a trench of the semiconductor body, at the top side of which the source/drain regions are formed by introduction of dopant. The gate dielectric, in which the storage layer sequence, for example an ONO storage layer sequence, is present, is situated between the gate electrode and the semiconductor material. The channel region extends around the trench bottom proceeding from the interfaces of the source/drain regions (junctions), thereby achieving a significantly longer channel length than in the case of a planar component. However, this gives rise to the problem that, on account of the non-rectilinear current flow, the electric field maximum does not occur at the interface (unction) of the drain region and, therefore, a targeted programming of a bit in the region of the drain is not ensured. In the case of previous trench transistors, the high field strengths required for programming and erasing the memory cells may lead to a complete depletion of the regions between two adjacent memory cells. In these intermediate regions, it is then no longer possible to control the direction of the hot charge carriers.
The storage layer of a charge trapping memory cell is situated between boundary layers made of a material having a higher energy band gap than the energy band gap of the storage layer, so that the charge carriers trapped in the storage layer remain localized there. A nitride is preferably appropriate as material for the storage layer; an oxide is primarily suitable as the surrounding material. In the example of such an oxide-nitride-oxide (ONO) storage layer sequence in the silicon material system, the storage layer is silicon nitride with an energy band gap of approximately 5 eV; the surrounding boundary layers are silicon oxide with an energy band gap of approximately 9 eV. The storage layer may be a different material whose energy band gap is smaller than the energy band gap of the boundary layers, the difference between the energy band gaps being intended to be as large as possible for good electrical confinement of the charge carriers. In conjunction with silicon oxide as boundary layers, it is possible to use, e.g., tantalum oxide, hafnium silicate, titanium oxide (in the case of stoichiometric composition TiO2), zirconium oxide (in the case of stoichiometric composition ZrO2), aluminum oxide (in the case of stoichiometric composition Al2O3) or intrinsically conducting (undoped) silicon as material of the storage layer.
The literature discloses programming memory cells by the so-called method of source-side injection. This requires two gate electrodes electrically insulated from one another. By virtue of the fact that the two gate electrodes are driven with electrical voltages that differ significantly from one another, the electric field maximum can be localized to the junction region between the two gate electrodes, so that it is thereby possible to achieve a targeted injection of charge carriers in this region. The literature specified in this respect shall include the publications by G. Groeseneken et al., Basics of Nonvolatile Semiconductor Memory Devices, in W. Brown and J. Brewer, Nonvolatile Semiconductor Memory Technology, IEEE Press, New York, 1998, pages 21 to 22, and H. Tomiye et al., A novel 2-bit/cell MONOS memory device with a wrapped-control-gate structure that applies source-side hot-electron injection.